1 mn103sj7/n0/n1/n2/n4/n5/n6 series 32-bit single-chip microcontroller ? overview the mn103s is a 32-bit microcontroller combining ease of use intended for programs development in the c language with a simple, high-performance architecture made possible through pursuit of cost performance. built around a compact 32-bit cpu with a basic instruction word length of 1 byte, this lsi includes internal memory for instructions and data, dma controller, a clock generator, bus controller, interrupt controller, watchdog timer, standard peripheral circuitry such as timers and serial interfaces, pwm circuit best suited to controlling 3-phase motors and a/d converters for motor position control. the mn103s series' high-speed cpu coupled with abundance of peripheral features provides an easy means of developing low-cost, high-performance and multifunctional system on lsi for motor and power control applications requiring fast response - a feature previously unavailable with conventional microcontrollers. ? product summary this datasheet describes the following model. model rom size ram size pins timer (8bit/ 16bit) pwm serial i/f a/d vga package MN103SFJ7A 32 kb 2 kb tqfp48 8/1 1 2 2 tqfp48-p-0707b mn103sfn0d 64 kb 4kb qfp44 tqfp48 8/2 1 2 2 qfp044-p-1010f tqfp48-p-0707b mn103sfn0x 8 kb mn103sfn0g 128 kb 6 kb mn103sfn0y 8 kb mn103sfn1d 64 kb 4 kb tqfp64 12/3 2 3 2 tqfp064-p-1010c mn103sfn1x 8 kb mn103sfn1g 128 kb 6 kb mn103sfn1y 8 kb mn103sfn2d 64 kb 4 kb tqfp80 12/5 2 3 2 tqfp080-p-1212d mn103sfn2x 8 kb mn103sfn2g 128 kb 6 kb mn103sfn2y 8 kb mn103sfn4d 64 kb 4 kb qfp44 tqfp48 8/2 1 2 2 1 qfp044-p-1010f tqfp48-p-0707b mn103sfn4x 8 kb mn103sfn4g 128 kb 6 kb mn103sfn4y 8 kb mn103sfn5d 64 kb 4 kb tqfp64 12/3 2 3 2 2 tqfp064-p-1010c mn103sfn5x 8 kb mn103sfn5g 128 kb 6 kb mn103sfn5y 8 kb mn103sfn6d 64 kb 4 kb tqfp80 12/5 2 3 2 2 tqfp080-p-1212d mn103sfn6x 8 kb mn103sfn6g 128 kb 6 kb mn103sfn6y 8 kb ver. dem publication date: september 2013
2 ? features ? cpu core mn103s core 4 gb of address space (for instructions / data) load/store architecture with 5-stage pipeline 46 basic instructions + 8 extension instructions 6 addressing modes instruction set of 1 byte in word length extension arithmetic unit incorporated (high-speed multiply instruction, high-speed division instruction etc.) machine cycle: 16.7 ns (oscillation frequency: 10 mhz, 6 multiplying) operation mode: normal mode, sellp mode, halt mode, stop mode ? oscillation circuit external oscillation (crystal/ ceramic) clock multiply circuit oscillation clock can be multiplied by from 3 to 12 ? internal memory rom: 32 k/64 k/128 k bytes ram: 2 k/4 k/6 k/8 k bytes the rom/ram size is different in each product. please refer to [ ? product summary] for details. ? dma controller number of channels: 1 channel startup sources: 15 sources (mn103sfn0/n4 series) 20 sources (mn103sfn1/n5 series) 22 sources (mn103sfn2/n6 series) (external interrupts: max 12 sources, serial interface: max 9 sources, software start: 1 source) transfer modes: 3 modes (one word transfer, burst transfer, intermittent transfer) *: there is not the function in the MN103SFJ7A. ? interrupts non-maskable interrupts watchdog timer over?ow interrupts system error interrupts fail safe function interrupts internal interrupts (level interrupt) MN103SFJ7A : 23 interrupts mn103sfn0/n4 series: 29 interrupts mn103sfn1/n5 series: 42 interrupts mn103sfn2/n6 series: 48 interrupts timer 0 under?ow interrupt timer 1 under?ow interrupt timer 2 under?ow interrupt timer 3 under?ow interrupt timer 4 under?ow interrupt timer 5 under?ow interrupt timer 6 under?ow interrupt timer 7 under?ow interrupt timer 8 under?ow interrupt timer 9 under?ow interrupt timer 10 under?ow interrupt timer 11 under?ow interrupt timer 16 over?ow/under?ow interrupt timer 16 compare/capture a interrupt ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
3 ? features (continued) (continued) timer 16 compare/capture b interrupt timer 17 over?ow/under?ow interrupt timer 17 compare/capture a interrupt timer 17 compare/capture b interrupt timer 18 over?ow/under?ow interrupt timer 18 compare/capture a interrupt timer 18 compare/capture b interrupt timer 19 over?ow/under?ow interrupt timer 19 compare/capture a interrupt timer 19 compare/capture b interrupt timer 20 over?ow/under?ow interrupt timer 20 compare/capture a interrupt timer 20 compare/capture b interrupt serial 0 reception end interrupts serial 0 communication/transmission end interrupts serial 1 reception end interrupts serial 1 communication/transmission end interrupts serial 2 reception end interrupts serial 2 communication/transmission end interrupts pwm0 over?ow interrupts pwm0 under?ow interrupts pwm0 synchronous a/d start a pwm0 synchronous a/d start b pwm1 over?ow interrupts pwm1 under?ow interrupts pwm1 synchronous a/d start a pwm1 synchronous a/d start b a /d 0 conversion end interrupt a /d 0 conversion end b interrupt a /d 1 conversion end interrupt a /d 1 conversion end b interrupt dma transfer end interrupt dma request after dma transfer end interrupt dma transfer request over?ow interrupt external interrupts: MN103SFJ7A : 4 interrupts mn103sfn0/n4 series : 8 interrupts mn103sfn1/n5 series : 10 interrupts mn103sfn2/n6 series : 12 interrupts external interrupt pins : from irq00 to irq11 interrupt detection condition : each edge, both edges, high-level and low-level detection each interrupt detection condition is able to ?ltering with the noise ?lter ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
4 ? features (continued) ? timer counter 8-bit timer 8 sets (MN103SFJ7A, mn103sfn0/n4 series) 12 sets (mn103sfn1/n5, mn103sfn2/n6 series) 16-bit timer 1 sets (MN103SFJ7A) 2 sets (mn103sfn0/n4 series) 3 sets (mn103sfn1/n5 series) 5 sets (mn103sfn2/n6 series) timer 0 (8-bit timer) interval timer, timer pulse output, event count, baud rate timer count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm0io pin input, timer 1 under?ow, timer 2 under?ow timer 1 (8-bit timer) interval timer, timer pulse output, event count, baud rate timer, cascade connection (connected to timer 0) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm1io pin input, timer 0 under?ow, timer 2 under?ow timer 2 (8-bit timer) interval timer, timer pulse output * 1 , event count * 1 , baud rate timer, cascade connection (connected to timer 1) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm2io pin input * 1 , timer 0 under?ow, timer 1 under?ow timer 3 (8-bit timer) interval timer, timer pulse output * 1 , event count * 1 , baud rate timer, cascade connection (connected to timer 2) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm3io pin input * 1 , timer 0 under?ow, timer 1 under?ow, timer 2 under?ow timer 4 (8-bit timer) interval timer, timer pulse output, event count count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm4io pin input, timer 5 under?ow, timer 6 under?ow timer 5 (8-bit timer) interval timer, timer pulse output, event count, cascade connection (connected to timer 4) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm5io pin input, timer 4 under?ow, timer 6 under?ow timer 6 (8-bit timer) interval timer, timer pulse output, event count, cascade connection (connected to timer 5) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm6io pin input, timer 4 under?ow, timer 5 under?ow timer 7 (8-bit timer) interval timer, timer pulse output, event count, cascade connection (connected to timer 6) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm7io pin input, timer 4 under?ow, timer 5 under?ow, timer 6 under?ow timer 8 (8-bit timer ) * 2 interval timer, timer pulse output * 3 , event count * 3 count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm8io pin input * 3 , timer 9 under?ow, timer 10 under?ow ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
5 ? features (continued) ? timer counter (continued) timer 9 (8-bit timer) * 2 interval timer, timer pulse output * 3 , event count * 3 , cascade connection (connected to timer 8) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm9io pin input * 3 , timer 8 under?ow, timer 10 under?ow timer 10 (8-bit timer) * 2 interval timer, timer pulse output, event count, cascade connection (connected to timer 9) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm10io pin input, timer 8 under?ow, timer 9 under?ow timer 11 (8-bit timer) * 2 interval timer, timer pulse output, event count, cascade connection (connected to timer 10) count clock source : ioclk, ioclk/8, ioclk/32, ioclk/128, tm11io pin input, timer 8 under?ow, timer 9 under?ow, timer 10 under?ow timer 16 (16-bit timer) interval timer, event count, up/down count, timer output, pwm output, input capture, one-shot output, external trigger start start by pwmn over?ow interrupt, pmwn under?ow interrupt, a/d conversion start trigger generation count clock source : ioclk, ioclk/8, timer 6 under?ow, timer 7 under?ow, tm16bio pin input timer 17 (16-bit timer) * 2 , * 4 interval timer, event count, up/down count, timer output, pwm output, input capture, one-shot output, external trigger start count clock source : ioclk, ioclk/8, ioclk/64, timer 11 under?ow, tm17bio pin input timer 18 (16-bit timer) * 5 interval timer, event count, up/down count, timer output, pwm output (output to 6 ports all at once is possible), input capture, one-shot output, external trigger start count clock source : ioclk, ioclk/8, ioclk/64, timer 7 under?ow, tm18bio pin input timer 19 (16-bit timer) * 2 interval timer, event count, up/down count, timer output, pwm output, input capture, one-shot output, external trigger start start by pwmn over?ow interrupt, pwmn under?ow interrupt, a/d conversion start trigger generation count clock source : ioclk, ioclk/8, timer 10 under?ow, timer 11 under?ow, tm19bio pin input timer 20 (16-bit timer) * 2 , * 4 interval timer, event count, up/down count, timer output, pwm output, input capture, one-shot output, external trigger start, count clock source : ioclk, ioclk/8, timer 6 under?ow, timer 7 under?ow, tm20bio pin input note) * 1: the function using the tmnio pin (n = 2, 3) cannot be used by the mn103sfn0/n4 series. * 2: there is not the function in the mn103sfn0/n4 series. * 3: the function using the tmnio pin (n = 8, 9) cannot be used by the mn103sfn1/n5 series. * 4: there is not the function in the mn103sfn1/n5 series. * 5: there is not the function in the mn103sj7a. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
6 ? features (continued) ? watchdog timer detection time 6.55 ms to 1677.72 ms (oscillation frequency 10 mhz) generates non-maskable interrupt at detection generates hard-reset at second consective over?ow ? a /d converter a/d0 resolution 10 bits minimum conversion time 0.5 m s analog input 5 channels (ad0in00 to ad0in04) a/d conversion start trigger is in synchronization with complementary 3-phase pwm cycle and 16-bit timer a/d1 resolution 10 bits minimum conversion time 0.5 m s analog input MN103SFJ7A : 3 channels (ad1in00 to ad1in02) mn103sfn0/n4 series: 3 channels (ad1in00 to ad1in02) mn103sfn1/n5 series: 7 channels (ad1in00 to ad1in06) mn103sfn2/n6 series: 11 channels (ad1in00 to ad1in10) a/d conversion start trigger is in synchronization with complementary 3-phase pwm cycle and 16-bit timer ? complementary 3-phase pwm output min. resolution: 16.7 ns triangular and saw-tooth waves output incorporates a dead time insertion circuit can overwrite registers by double buffer during pwm operation pwm output protection circuit supporting external interrupts and non-maskable interrupt output timing varying function a/d conversion start trigger, 16-bit timer start trigger ? vga vga mn103sfn4 series 1 sets mn103sfn5/n6 series 2 sets the gain of eight stages can be set (2.05, 3.03, 4.00, 4.98, 5.96, 7.90, 9.83, and 19.40times) offset voltage cancel cansel function(short-circuit or switching) ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
7 ? features (continued) ? serial interface 3 channels serial 0 (full duplex uart / synchronous serial interface) synchronous serial interface overrun error detection transfer clock source: 1/2, 1/4, 1/16 and 1/64 of timer 0 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 1 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 2 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 3 under?ow, ioclk/2, ioclk/4, sbt0 pin can be selected as the ?rst bit to be transferred, any transfer size from 2 to 8 bits can be selected. can be continuously transmitted, received or transmitted and received. maximum transfer rate: 5.0 mbps full duplex uart parity check, overrun and ?aming error detection transfer clock source: 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 0 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 1 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 2 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 3 und er?ow, ioclk/16, ioclk/32, ioclk/64 can be selected as the ?rst bit to be transferred, any transfer size from 7 to 8 bits can be selected. continuous transmission, reception, and transmission/reception maximum transfer rate: 300 kbps serial 1 (full duplex uart / synchronous serial interface) synchronous serial interface overrun error detection transfer clock source: 1/2, 1/4, 1/16 and 1/64 of timer 0 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 1 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 2 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 3 under?ow, ioclk/2, ioclk/4, sbt1 pin can be selected as the ?rst bit to be transferred, any transfer size from 2 to 8 bits can be selected. continuous transmission, reception, and transmission/reception maximum transfer rate: 5.0 mbps full duplex uart parity check, overrun and ?aming error detection transfer clock source: 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 0 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 1 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 2 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 3 und er?ow, ioclk/16, ioclk/32, ioclk/64 can be selected as the ?rst bit to be transferred, any transfer size from 7 to 8 bits can be selected. continuous transmission, reception, and transmission/reception maximum transfer rate: 300 kbps ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
8 ? features (continued) serial 2 (full duplex uart / synchronous serial interface) synchronous serial interface overrun error detection transfer clock source 1/2, 1/4, 1/16 and 1/64 of timer 0 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 1 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 2 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 3 under?ow, ioclk/2, ioclk/4, sbt2 pin can be selected as the ?rst bit to be transferred, any transfer size from 2 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 5.0 mbps corresponding to the 4 channel system communication and the spi communication full duplex uart parity check, overrun and ?aming error detection transfer clock source 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 0 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 1 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 2 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 3 und er?ow, ioclk/16, ioclk/32, ioclk/64 can be selected as the ?rst bit to be transferred, any transfer size from 7 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 300 kbps ? regulator incorporates regulator, and use of 5 v power supply is possible ? power supply detection detection level 3.6 v to 4.3 v when power supply voltage is under detection level, reset is generated. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
8 ? features (continued) serial 2 (full duplex uart / synchronous serial interface) synchronous serial interface overrun error detection transfer clock source 1/2, 1/4, 1/16 and 1/64 of timer 0 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 1 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 2 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 3 under?ow, ioclk/2, ioclk/4, sbt2 pin can be selected as the ?rst bit to be transferred, any transfer size from 2 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 5.0 mbps corresponding to the 4 channel system communication and the spi communication full duplex uart parity check, overrun and ?aming error detection transfer clock source 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 0 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 1 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 2 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 3 und er?ow, ioclk/16, ioclk/32, ioclk/64 can be selected as the ?rst bit to be transferred, any transfer size from 7 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 300 kbps ? regulator incorporates regulator, and use of 5 v power supply is possible ? power supply detection detection level 3.6 v to 4.3 v when power supply voltage is under detection level, reset is generated. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
8 ? features (continued) serial 2 (full duplex uart / synchronous serial interface) synchronous serial interface overrun error detection transfer clock source 1/2, 1/4, 1/16 and 1/64 of timer 0 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 1 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 2 under?ow, 1/2, 1/4, 1/16 and 1/64 of timer 3 under?ow, ioclk/2, ioclk/4, sbt2 pin can be selected as the ?rst bit to be transferred, any transfer size from 2 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 5.0 mbps corresponding to the 4 channel system communication and the spi communication full duplex uart parity check, overrun and ?aming error detection transfer clock source 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 0 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 1 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 2 und er?ow, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 and 1/1024 of timer 3 und er?ow, ioclk/16, ioclk/32, ioclk/64 can be selected as the ?rst bit to be transferred, any transfer size from 7 to 8 bits can be selected. continuous transmission, reception and transmission / reception maximum transfer rate: 300 kbps ? regulator incorporates regulator, and use of 5 v power supply is possible ? power supply detection detection level 3.6 v to 4.3 v when power supply voltage is under detection level, reset is generated. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
11 ? pin description ? MN103SFJ7A ( tqfp048-p-0707b) ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
12 ? pin description (continued) ? mn103sfn0/n4 series ( qfp044-p-1010f) 25 24 tm1io/irq01/p01 vout18 nboot sdat a 20 40 39 38 37 p50/tm16aio/tm18o2/irq10 36 35 34 44 43 42 41 p85/npwm0 2 vdd5 0 vs s p60/tm18aio/tm18o4 p61/tm18bio/tm18o5 11 test 8 9 ad1in02/pc 7 10 ad1in01/pc 6 ad0in04/pc4 ad1in00/pc 5 avs s ad0in03/pc3 6 7 avdd5 0 p82/pwm0 1 p81/npwm0 0 * vga0(+)/ad0in0 0 5 4 1 3 2 * vga0(-)/ad0in0 1 ad0in02/pc2 p80/pwm0 0 30 p51/tm16bio/tm18o3/irq11 33 32 31 mn103sfn0/n4 series 27 p84/pwm0 2 p83/npwm0 1 14 15 p22/sbi0 p41/tm7io/tm18o1/irq09 p40/tm6io/tm18o0/irq08 p25/sbi1 p24/sbt1 p23/sbo1 28 29 p21/sbt0 vs s vdd5 0 nrst osco osci 19 26 qfp 44pin 0.8mm pitc h sclk p20/sbo0 21 22 p03/irq03/tm5io/extrg0 tm0io/irq00/p00 16 12 13 p02/irq02/tm4io/extrg1 17 18 23 * vga is not in the mn103sfn0 series. 1,2 pin of mn103sfn0 series are the dedicated input pin for a/d converter. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
13 ? pin description (continued) ? mn103sfn0/n4 series ( tqfp048-p-0707b) mn103sfn0/n4 series tqfp 48pin 0.5mm pitch * vga is not in the mn103sfn0 series. 1,2 pin of mn103sfn0 series are the dedicated input pin for a/d converter. 18 nboot sclk tm1io/irq01/p0 1 vout18 sdat a 44 43 42 41 p50/tm16aio/tm18o2/irq1 0 40 39 37 48 47 46 45 p85/npwm0 2 vdd5 0 vs s p60/tm18aio/tm18o4 p61/tm18bio/tm18o5 12 test 8 9 6 7 avdd5 0 n.c. 10 ad1in01/pc6 ad0in04/pc4 ad1in00/pc5 11 ad1in02/pc7 vga0(+)/ad0in0 0 5 4 1 3 2 vga0(-)/ad0in0 1 ad0in02/pc2 avs s ad0in03/pc3 31 p84/pwm0 2 p83/npwm0 1 p82/pwm0 1 p81/npwm0 0 32 p80/pwm0 0 33 p51/tm16bio/tm18o3/irq11 36 35 34 38 osci p20/sbo0 22 24 25 p02/irq02/tm4io/extrg 1 21 20 13 14 15 16 p21/sbt0 23 n.c. 26 p03/irq03/tm5io/extrg 0 28 27 nrst n.c. p22/sbi0 p23/sbo1 p41/tm7io/tm18o1/irq09 p40/tm6io/tm18o0/irq08 30 29 n.c. p25/sbi1 p24/sbt1 osco tm0io/irq00/p0 0 17 vs s vdd5 0 19 ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
14 ? pin description (continued) ? mn103sfn1/n5 series ( tqfp064-p-1010c) 53 58 57 56 55 61 60 59 54 47 46 45 36 37 39 sbo0/p20 p42/tm2io/irq1 0 p41/tm7io/tm18o1/irq09 p40/tm6io/tm18o0/irq08 p33/sbcs2 p24/sbt1 p25/sbi 1 p30/sbo 2 p32/sbi 2 p31/sbt2 sbt0/p21 32 vs s osco osci vdd5 0 29 nboot 30 tm0io/irq00/p00 tm1io/irq01/p01 extrg1/tm4io/irq02/p02 extrg0/tm5io/irq03/p03 sclk sdat a vout18 test 17 18 19 20 23 24 31 28 p46/tm10io/irq04 p50/tm16aio/tm18o2 p47/tm11io/irq05 p43/tm3io/irq1 1 p81/npwm0 0 p80/pwm0 0 35 34 38 40 43 42 44 41 48 p51/tm16bio/tm18o3 52 51 50 49 p83/npwm0 1 p82/pwm0 1 p85/npwm0 2 p84/pwm0 2 p93/npwm1 1 p92/pwm1 1 p91/npwm1 0 p90/pwm1 0 ad1in06/pd 3 tqfp 64pin 0.5mm pitc h ad1in01/pc 6 16 ad1in05/pd 2 * vga1(+)/ad1in03 14 15 * vga1(-)/ad1in04 13 ad1in02/pc 7 ad1in00/pc 5 avs s ad0in03/pc3 avdd5 0 12 10 11 8 * vga0(-)/ad0in01 ad0in02/pc2 9 6 7 ad0in04/pc4 5 4 * vga0(+)/ad0in00 tm19aio/p6 4 tm19bio/p6 5 1 3 2 22 vdd5 0 vs s p60/tm18aio/tm18o4 p61/tm18bio/tm18o5 p95/npwm1 2 64 63 62 p94/pwm1 2 mn103sfn1/n5 series p22/sbi 0 nrst p23/sbo 1 21 25 26 33 27 * vga is not in the mn103sfn1 series. 3,4,13,14 p in of mn103sfn1 series are the dedicated in p ut p in for a/d converter. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
15 ? pin description (continued) ? mn103sfn2/n6 series ( tqfp080-p-1212d) 73 61 70 69 68 67 72 71 64 63 tqfp 80pin 0.5mm pitch irq04/p0 4 irq07/p0 7 osco osci nrst nboot irq05/p0 5 irq06/p0 6 sclk sbo0/p20 sbt0/p21 39 32 33 vdd5 0 36 34 35 38 tm0io/irq00/p00 tm1io/irq01/p01 extrg1/tm4io/irq02/p02 extrg0/tm5io/irq03/p03 sdat a vout18 test vs s 26 27 28 37 55 21 22 23 24 40 25 29 30 31 p45/tm9i o p33/sbcs2 51 50 p42/tm2io/irq1 0 p41/tm7io/tm18o1/irq09 p40/tm6io/tm18o0/irq08 54 48 p22/sbi 0 ad1in10/pd 7 41 20 ad1in09/pd 6p 23/sbo 1 43 42 18 19 ad1in08/pd 5 p25/sbi 1 p24/sbt1 p30/sbo 2 45 44 p47/tm11io 47 46 p43/tm3io/irq1 1 p44/tm8i o 52 53 p32/sbi 2 49 p31/sbt2 p46/tm10io vs s p51/tm16bio/tm18o3 60 p50/tm16aio/tm18o2 56 vdd5 0 59 58 57 62 p84/pwm0 2 p83/npwm0 1 66 65 p54/tm17ai o p82/pwm0 1 p81/npwm0 0 p80/pwm0 0 p55/tm17bi o p85/npwm0 2 p94/pwm1 2 ad1in07/pd 4 16 ad1in06/pd 3 17 * vga1(+)/ad1in03 13 * vga1(-)/ad1in04 80 79 78 77 76 ad1in00/pc 5 10 15 12 ad1in05/pd 2 ad1in01/pc 6 ad1in02/pc 7 11 14 avs s 9 ad0in03/pc3 6 7 avdd5 0 ad0in04/pc4 8 * vga0(-)/ad0in01 ad0in02/pc2 tm19aio/p6 4 5 4 1 3 2 tm19bio/p6 5 * vga0(+)/ad0in00 p91/npwm1 0 vout18 p61/tm18bio/tm18o5 vs s pb1/tm20bi o mn103sfn2/n 6 series p60/tm18aio/tm18o4 pb0/tm20ai o p95/npwm1 2 p90/pwm1 0 75 74 p93/npwm1 1 p92/pwm1 1 * vga is not in the mn103sfn2 series. 3,4,13,14 pin of mn103sfn2 series are the dedicated input pin for a/d converter. ver. dem mn103sj7/n0/n1/n2/n4/n5/n6 series
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